A3968
Dual Full-Bridge PWM Motor Driver with Brake
Features
- ±650 mA continuous output current
- 30 V output voltage rating
- Internal fixed-frequency PWM current control
- Satlington? sink drivers
- Brake mode
- User-selectable blanking window
- Internal ground-clamp and flyback diodes
- Internal thermal-shutdown circuitry
- Crossover-current protection and UVLO protection
Description
The A3968 bidirectionally controls two DC motors. The device includes two full-bridges capable of continuous output currents of ±650 mA and operating voltages to 30 V. Motor winding current can be controlled by the internal fixed-frequency, pulse-width modulated (PWM), current-control circuitry. The peak load current limit is set by user selection of a reference voltage and current-sensing resistors.
The fixed-frequency pulse duration is set by a user-selected external RC timing network. The capacitor in the RC timing network also determines a user-selectable blanking window that prevents false triggering of the PWM current-control circuitry during switching transitions.
To reduce on-chip power dissipation, the full-bridge power outputs have been optimized for low saturation voltages. The sink drivers feature the Allegro? patented Satlington? output structure. The Satlington outputs combine the low voltage drop of a saturated transistor and the high peak current capability of a Darlington.
For each bridge, the INPUTA and INPUTB terminals determine the load-current polarity by enabling the appropriate source and sink driver pair. When a logic low is applied to both INPUTs of a bridge, the braking function is enabled. In brake mode, both source drivers are turned off and both sink drivers are turned on, thereby dynamically braking the motor. When a logic high is applied to both INPUTs of a bridge, all output drivers are disabled.
Special power-up sequencing is not required. Internal circuit protection includes thermal shutdown with hysteresis, ground-clamp and flyback diodes, and crossover-current protection.
The A3968 is supplied in a 16-lead plastic SOIC with two pins internally fused to the die pad for enhanced thermal dissipation. These pins are at ground potential and need no electrical isolation. The device is lead (Pb) free, with 100% matte tin leadframe plating.
Functional Block Diagram